Coreinfo v2.0
By Mark Russinovich
Published: October 21, 2009
Download Coreinfo (908 KB)
Introduction
Coreinfo is a command-line utility that shows you the mapping between logical processors and the physical processor, NUMA node, and socket on which they reside, as well as the cache’s assigned to each logical processor. It uses the Windows’ GetLogicalProcessorInformation function to obtain this information and prints it to the screen, representing a mapping to a logical processor with an asterisk e.g. ‘*’. Coreinfo is useful for gaining insight into the processor and cache topology of your system.
Installation
You run Coreinfo by typing "coreinfo”.
Using CoreInfo
Usage: coreinfo [-c][-g][-l][-n][-s]
| -c | Dump information on cores. |
| -g | Dump information on groups. |
| -l | Dump information on caches. |
| -n | Dump information on NUMA nodes. |
| -s | Dump information on sockets. |
Coreinfo Output:
The following output is from an 2-socket, quad-core system, AMD Opteron system. Note how each socket corresponds to a NUMA node, and each CPU has its own L1 instruction and data cache and L2 unified cache.
Coreinfo v1.00 - Dump information on CPU cores, NUMA nodes, sockets and caches
Copyright (C) 2008 Mark Russinovich
Sysinternals - www.sysinternals.com
Logical to Physical Processor Map:
*------- Physical Processor 0
-*------ Physical Processor 1
--*----- Physical Processor 2
---*---- Physical Processor 3
----*--- Physical Processor 4
-----*-- Physical Processor 5
------*- Physical Processor 6
-------* Physical Processor 7
Logical Processor to Socket Map:
****---- Socket 0
----**** Socket 1
Logical Processor to NUMA Node Map:
****---- NUMA Node 0
----**** NUMA Node 1
Logical Processor to Cache Map:
*------- Data Cache 0, Level 1, 64 KB, Assoc 2 LineSize: 64
*------- Instruction Cache 0, Level 1, 64 KB, Assoc 2 LineSize: 64
*------- Unified Cache 0, Level 2, 512 KB, Assoc 16 LineSize: 64
-*------ Data Cache 1, Level 1, 64 KB, Assoc 2 LineSize: 64
-*------ Instruction Cache 1, Level 1, 64 KB, Assoc 2 LineSize: 64
-*------ Unified Cache 1, Level 2, 512 KB, Assoc 16 LineSize: 64
--*----- Data Cache 2, Level 1, 64 KB, Assoc 2 LineSize: 64
--*----- Instruction Cache 2, Level 1, 64 KB, Assoc 2 LineSize: 64
--*----- Unified Cache 2, Level 2, 512 KB, Assoc 16 LineSize: 64
---*---- Data Cache 3, Level 1, 64 KB, Assoc 2 LineSize: 64
---*---- Instruction Cache 3, Level 1, 64 KB, Assoc 2 LineSize: 64
---*---- Unified Cache 3, Level 2, 512 KB, Assoc 16 LineSize: 64
----*--- Data Cache 4, Level 1, 64 KB, Assoc 2 LineSize: 64
----*--- Instruction Cache 4, Level 1, 64 KB, Assoc 2 LineSize: 64
----*--- Unified Cache 4, Level 2, 512 KB, Assoc 16 LineSize: 64
-----*-- Data Cache 5, Level 1, 64 KB, Assoc 2 LineSize: 64
-----*-- Instruction Cache 5, Level 1, 64 KB, Assoc 2 LineSize: 64
-----*-- Unified Cache 5, Level 2, 512 KB, Assoc 16 LineSize: 64
------*- Data Cache 6, Level 1, 64 KB, Assoc 2 LineSize: 64
------*- Instruction Cache 6, Level 1, 64 KB, Assoc 2 LineSize: 64
------*- Unified Cache 6, Level 2, 512 KB, Assoc 16 LineSize: 64
-------* Data Cache 7, Level 1, 64 KB, Assoc 2 LineSize: 64
-------* Instruction Cache 7, Level 1, 64 KB, Assoc 2 LineSize: 64
-------* Unified Cache 7, Level 2, 512 KB, Assoc 16 LineSize: 64
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